SA-1 Write Registers
| Register | Address | Name | Notes |
|---|
| SA-1 CPU Control | $2200 | CCNT | |
| Super Nintendo CPU INT Enable | $2201 | SIE | |
| Super Nintendo CPU INT Clear | $2202 | SIC | |
| SA-1 CPU Reset Vector | $2203 | CRVL | \ Bits 0-7 |
| SA-1 CPU Reset Vector | $2204 | CRVH | / Bits 8-15 |
| SA-1 CPU NMI Vector | $2205 | CNVL | \ Bits 0-7 |
| SA-1 CPU NMI Vector | $2206 | CNVH | / Bits 8-15 |
| SA-1 CPU IRQ Vector | $2207 | CIVL | \ Bits 0-7 |
| SA-1 CPU IRQ Vector | $2208 | CIVH | / Bits 8-15 |
| Super Nintendo CPU Control | $2209 | SCNT | |
| SA-1 CPU INT Enable | $220A | CIE | |
| SA-1 CPU INT Clear | $220B | CIC | |
| Super Nintendo CPU NMI Vector | $220C | SNVL | \ Bits 0-7 |
| Super Nintendo CPU NMI Vector | $220D | SNVH | / Bits 8-15 |
| Super Nintendo CPU IRQ Vector | $220E | SIVL | \ Bits 0-7 |
| Super Nintendo CPU IRQ Vector | $220F | SIVH | / Bits 8-15 |
| H/V Timer Control | $2210 | TMC | |
| SA-1 CPU Timer Restart | $2211 | CTR | |
| Set H-Count | $2212 | HCNTL | \ Bits 0-7 |
| Set H-Count | $2213 | HCNTH | / Bits 8-15 (Only Bit 8 used) |
| Set V-Count | $2214 | VCNTL | \ Bits 0-7 |
| Set V-Count | $2215 | VCNTH | / Bits 8-15 (Only Bit 8 used) |
| Set Super MMC Bank C | $2220 | CXB | |
| Set Super MMC Bank D | $2221 | DXB | |
| Set Super MMC Bank E | $2222 | EXB | |
| Set Super MMC Bank F | $2223 | FXB | |
| Super Nintendo CPU BW-RAM Address Mapping | $2224 | BMAPS | |
| SA-1 CPU BW-RAM Address Mapping | $2225 | BMAP | |
| Super Nintendo CPU BW-RAM Write Enable | $2226 | SBWE | |
| SA-1 CPU BW-RAM Write Enable | $2227 | CBWE | |
| BW-RAM Write-Protected Area | $2228 | BWPA | |
| SA-1 I-RAM Write Protection | $2229 | SIWP | \ S-CPU Controlled |
| SA-1 I-RAM Write Protection | $222A | CIWP | / SA-1 Controlled |
| DMA Control | $2230 | DCNT | |
| Character Conversion DMA Parameters | $2231 | CDMA | |
| DMA Source Device Start Address | $2232 | SDAL | \ Bits 0-7 |
| DMA Source Device Start Address | $2233 | SDAH | ! Bits 8-15 |
| DMA Source Device Start Address | $2234 | SDAB | / Bits 16-23 |
| DMA Destination Start Address | $2235 | DDAL | \ Bits 0-7 |
| DMA Destination Start Address | $2236 | DDAH | ! Bits 8-15 |
| DMA Destination Start Address | $2237 | DDAB | / Bits 16-23 |
| DMA Terminal Counter | $2238 | DTCL | \ Bits 0-7 |
| DMA Terminal Counter | $2239 | DTCH | / Bits 8-15 |
| BW-RAM BIT MAP Format | $223F | BBF | |
| BIT MAP Register File | $2240 | BRF0 | \ File 0 |
| BIT MAP Register File | $2241 | BRF1 | ! File 1 |
| BIT MAP Register File | $2242 | BRF2 | ! File 2 |
| BIT MAP Register File | $2243 | BRF3 | ! File 3 |
| BIT MAP Register File | $2244 | BRF4 | ! File 4 |
| BIT MAP Register File | $2245 | BRF5 | ! File 5 |
| BIT MAP Register File | $2246 | BRF6 | ! File 6 |
| BIT MAP Register File | $2247 | BRF7 | ! File 7 |
| BIT MAP Register File | $2248 | BRF8 | ! File 8 |
| BIT MAP Register File | $2249 | BRF9 | ! File 9 |
| BIT MAP Register File | $224A | BRFA | ! File A |
| BIT MAP Register File | $224B | BRFB | ! File B |
| BIT MAP Register File | $224C | BRFC | ! File C |
| BIT MAP Register File | $224D | BRFD | ! File D |
| BIT MAP Register File | $224E | BRFE | ! File E |
| BIT MAP Register File | $224F | BRFF | / File F |
| Arithmetic Control | $2250 | MCNT | |
| Arithmetic Parameters: Multiplicand / Dividend | $2251 | MAL | \ Bits 0-7 |
| Arithmetic Parameters: Multiplicand / Dividend | $2252 | MAH | / Bits 8-15 |
| Arithmetic Parameters: Multiplier / Divisor | $2253 | MBL | \ Bits 0-7 |
| Arithmetic Parameters: Multiplier / Divisor | $2254 | MBH | / Bits 8-15 |
| Variable-Length BIT Processing | $2258 | VBD | |
| Variable-Length BIT Game Pack ROM Start Address | $2259 | VDAL | \ Bits 0-7 |
| Variable-Length BIT Game Pack ROM Start Address | $225A | VDAH | ! Bits 8-15 |
| Variable-Length BIT Game Pack ROM Start Address | $225B | VDAB | / Bits 16-23 |
SA-1 Read Registers
| Register | Address | Name | Notes |
|---|
| Super Nintendo CPU Flag Read | $2300 | SFR | |
| SA-1 CPU Flag Read | $2301 | CFR | |
| H-Count Read | $2302 | HCRL | |
| H-Count Read | $2303 | HCRH | |
| V-Count Read | $2304 | VCRL | |
| V-Count Read | $2305 | VCRH | |
| Arithmetic Result Product / Quotient / Accumulative Sum | $2306 | MR1 | \ Bits 0-7 |
| Arithmetic Result Product / Quotient / Accumulative Sum | $2307 | MR2 | ! Bits 8-15 |
| Arithmetic Result Product / Quotient / Accumulative Sum | $2308 | MR3 | ! Bits 16-23 |
| Arithmetic Result Product / Quotient / Accumulative Sum | $2309 | MR4 | ! Bits 24-31 |
| Arithmetic Result Product / Quotient / Accumulative Sum | $230A | MR5 | / Bits 32-39 |
| Arithmetic Overflow Flag | $230B | OF | |
| Variable-Length Data Read Port | $230C | VDPL | \ Bits 0-7 |
| Variable-Length Data Read Port | $230D | VDPH | / Bits 8-15 |
| Version Code Register | $230E | VC | |
SA-1 Register Explanations
Register format(#$xx, write, read) xx = initial value (or xx for not specified)
W = SA-1 write
w = SNES write
X = Both
x = Neither
R = SA-1 Read
r = SNES Read
X = Both
x = Neither
SA-1 Write Registers
SA-1 CPU Control
$2200 (#$20, w, x)
IRrNmmmm
I = SA-1 IRQ
0 = No Interrupt
1 = Interrupt
R = SA-1 Ready
0 = Ready
1 = Wait
r = SA-1 reset
0 = Cancel
1 = Reset
N = SA-1 NMI
0 = No Interrupt
1 = Interrupt
mmmm = Messages from SNES CPU
Super Nintendo CPU INT Enable
$2201 (#$00, w, x)
I-C----
I = Enable/Disable IRQ from SA-1
0 = Disable
1 = Enable
C = Enable/Disable character conversion DMA IRQ
0 = Disable
1 = Enable
Super Nintendo CPU INT Clear
$2202 (#$00, w, x)
I-C----
I = clear IRQ from SA-1
0 = No change
1 = Change
C = clear character conversion DMA IRQ
0 = No change
1 = Clear
SA-1 CPU Reset Vector
$2203
$2204 (#$xxxx, w, x)
aaaaaaaa aaaaaaaa
a = SA-1 reset vector address(in bank $00)
SA-1 CPU NMI Vector
$2205
$2206 (#$xxxx, w, x)
aaaaaaaa aaaaaaaa
a = SA-1 NMI vector address(in bank $00)
SA-1 CPU IRQ Vector
$2207
$2208 (#$xxxx, w, x)
aaaaaaaa aaaaaaaa
a = SA-1 IRQ vector address(in bank $00)
Super Nintendo CPU Control
$2209 (#$00, W, x)
IS-Nmmmm
I = SNES IRQ
0 = No interrupt
1 = Interrupt
S = IRQ vector select
0 = ROM
1 = SNES IRQ register($220E)
N = NMI vector select
0 = ROM
1 = SNES NMI register($220C)
mmmm = Message from SA-1
SA-1 CPU INT Enable
$220A (#$00, W, x)
ITDN----
I = Switch IRQ control from SNES to SA-1
0 = Disable
1 = Enable
T = Switch IRQ control from timer to SA-1
0 = Disable
1 = Enable
D = Switch IRQ control to SA-1 after SA-1 DMA
0 = Disable
1 = Enable
N = Switch NMI control from SNES to SA-1
0 = Disable
1 = Enable
SA-1 CPU INT Clear
$220B (#$00, W, x)
ITDN----
I = Switch IRQ clear from SNES to SA-1
0 = Disable
1 = Enable
T = Switch IRQ clear from timer to SA-1
0 = Disable
1 = Enable
D = Switch IRQ clear to SA-1 after SA-1 DMA
0 = Disable
1 = Enable
N = Switch NMI clear from SNES to SA-1
0 = Disable
1 = Enable
Super Nintendo CPU NMI Vector
$220C
$220D (#$xxxx, w, x)
aaaaaaaa aaaaaaaa
a = SNES NMI vector address(in bank $00)
Super Nintendo CPU IRQ Vector
$220E
$220F (#$xxxx, w, x)
aaaaaaaa aaaaaaaa
a = SNES IRQ vector address(in bank $00)
H/V Timer Control
$2210 (#$00, W, x)
T-----VH
T = Timer type
0 = HV Timer
1 = Linear timer
V = Vertical count enable
0 = Disable
1 = Enable
H = Horizontal count enable
0 = Disable
1 = Enable
SA-1 CPU Timer Restart
$2211 (#$xx, W, x)
--------
Simply writing to this register restarts the timer to zero.
Set H-Count
$2212 (#$xxxx, W, x)
$2213
HHHHHHHH -------H
In HV mode values are 0 to 340
In linear mode values are 0 to 511(lower 9 bits)
Set V-Count
$2212 (#$xxxx, W, x)
$2213
VVVVVVVV -------V
In HV mode values are 0 to 261(NTSC) or 0 to 311(PAL)
In linear mode values are 0 to 511(upper 9 bits)
Set Super MMC Bank C
$2220 (#$00, w, x)
B----AAA
B = Bank CX projection
1 = Bank data
0 = Game pak ROM area
AAA = ROM area select
When B is set, accessing an address in $00-1F:8000-FFFF will return (AAA << 20) | (addr & 0x0F7FFF).
If B is not set accessing an address in $00-1F:8000-FFFF will return (addr & 0x0f7fff)
$C0-$CF:0000-FFFF will always return (AAA << 20) | (addr & 0x0FFFFF)
NOTE: I need to research this further, but this seems to prove accurate thus far.
Set Super MMC Bank D
$2221 (#$01, w, x)
B----AAA
B = Bank DX projection
1 = Bank data
0 = Game pak ROM area
AAA = ROM area select
When B is set, accessing an address in $20-3F:8000-FFFF will return (AAA << 20) | (addr & 0x0F7FFF).
If B is not set accessing an address in $20-3F:8000-FFFF will return (addr & 0x2f7fff)
$D0-$DF:0000-FFFF will always return (AAA << 20) | (addr & 0x0FFFFF)
NOTE: I need to research this further, but this seems to prove accurate thus far.
Set Super MMC Bank E
$2222 (#$02, w, x)
B----AAA
B = Bank EX projection
1 = Bank data
0 = Game pak ROM area
AAA = ROM area select
When B is set, accessing an address in $80-9F:8000-FFFF will return (AAA << 20) | (addr & 0x0F7FFF).
If B is not set accessing an address in $80-9F:8000-FFFF will return (addr & 0x4f7fff)
$E0-$EF:0000-FFFF will always return (AAA << 20) | (addr & 0x0FFFFF)
NOTE: I need to research this further, but this seems to prove accurate thus far.
Set Super MMC Bank F
$2223 (#$03, w, x)
B----AAA
B = Bank FX projection
1 = Bank data
0 = Game pak ROM area
AAA = ROM area select
When B is set, accessing an address in $A0-BF:8000-FFFF will return (AAA << 20) | (addr & 0x0F7FFF).
If B is not set accessing an address in $A0-BF:8000-FFFF will return (addr & 0x6f7fff)
$F0-$FF:0000-FFFF will always return (AAA << 20) | (addr & 0x0FFFFF)
NOTE: I need to research this further, but this seems to prove accurate thus far.
Super Nintendo CPU BW-RAM Address Mapping
$2224 (#$00, w, x)
---BBBBB
B = Which portion of BW-RAM to map to $00-3F:$6000-$7FFF and $80-BF:$6000-$7FFF
SA-1 CPU BW-RAM Address Mapping
$2225 (#$00, W, x)
SBBBBBBB
S = BW-RAM source to be projected
0 = $40-43 in 32 blocks(uses B0 to B4)
1 = $60-6F in 128 blocks(uses B0 to B6)
B = BW-RAM mapping for the SA-1(much like $2224)
Super Nintendo CPU BW-RAM Write Enable
$2226 (#$00, w, x)
P-------
P = Protect BW-RAM from writes from the SNES
0 = Protect
1 = Write enabled
SA-1 CPU BW-RAM Write Enable
$2227 (#$00, w, x)
P-------
P = Protect BW-RAM from writes from the SA-1
0 = Protect
1 = Write enabled
BW-RAM Write-Protected Area
$2228 (#$FF, w, x)
----AAAA
AAAA = Area to protect
0000 = Size of 400000 - 4000FF to protect, 1024*2^(AAAA+1)
SA-1 I-RAM Write Protection
$2229 (#$00, w, x)
76543210
0 = Protects 3000 to 30FF
0 = Disable protection
1 = Enable protection
1 = Protects 3100 to 31FF
0 = Disable protection
1 = Enable protection
2 = Protects 3200 to 32FF
0 = Disable protection
1 = Enable protection
3 = Protects 3300 to 33FF
0 = Disable protection
1 = Enable protection
4 = Protects 3400 to 34FF
0 = Disable protection
1 = Enable protection
5 = Protects 3500 to 35FF
0 = Disable protection
1 = Enable protection
6 = Protects 3600 to 36FF
0 = Disable protection
1 = Enable protection
7 = Protects 3700 to 37FF
0 = Disable protection
1 = Enable protection
SA-1 I-RAM Write Protection
$222A (#$00, W, x)
76543210
0 = Protects 3000 to 30FF and 0000 to 00FF
0 = Disable protection
1 = Enable protection
1 = Protects 3100 to 31FF and 0100 to 01FF
0 = Disable protection
1 = Enable protection
2 = Protects 3200 to 32FF and 0200 to 02FF
0 = Disable protection
1 = Enable protection
3 = Protects 3300 to 33FF and 0300 to 03FF
0 = Disable protection
1 = Enable protection
4 = Protects 3400 to 34FF and 0400 to 04FF
0 = Disable protection
1 = Enable protection
5 = Protects 3500 to 35FF and 0500 to 05FF
0 = Disable protection
1 = Enable protection
6 = Protects 3600 to 36FF and 0600 to 06FF
0 = Disable protection
1 = Enable protection
7 = Protects 3700 to 37FF and 0700 to 07FF
0 = Disable protection
1 = Enable protection
DMA Control
$2230 (#$00, W, x)
CPMT-DSS
C = DMA control
0 = DMA disabled
1 = DMA enabled
P = Priority
0 = SA-1 CPU
1 = DMA
M DMA mode
0 = Normal DMA
1 = Character conversion DMA
T = Character conversion type
0 = SA-1 CPU to I-RAM
1 = BW-RAM to I-RAM
D = Destination
0 = I-RAM
1 = BW-RAM
SS = Source
00 = ROM
01 = BW-RAM
10 = I-RAM
Character Conversion DMA Parameters
$2231 (#$00, X, x)
E--SSSCC
E = End of conversion 1, set by SNES
SSS = VRAM horizontal character size 2^SSS
CC = color mode
00 = 8 Bit/Dot
01 = 4 Bit/Dot
10 = 2 Bit/Dot
DMA Source Device Start Address
$2232
$2233
$2234 (#$xx, X, x)
AAAAAAAA AAAAAAAA AAAAAAAA
A = Source start address
Write in order low, middle, then high
DMA Destination Start Address
$2235
$2236
$2237 (#$xx, X, x)
AAAAAAAA AAAAAAAA AAAAAAAA
A = Destination start address
Writing to $2236 will initalize I-RAM DMA
Writing to $2237 will initalize BW-RAM DMA
Write in order low, middle, then high
DMA Terminal Counter
$2238
$2239 (#$xx, W, x)
CCCCCCCC CCCCCCCC
C = Counter for number of bytes to transmit (0 to 65535)
$223F (#$00, W, x)
C-------
C = color mode
0 = 16 color mode
1 = 4 color mode
BIT MAP Register File
$2240
$2241
$2242
$2243
$2244
$2245
$2246
$2247
$2248
$2249
$224A
$224B
$224C
$224D
$224E
$224F (#$xx, W, x)
$2240-2247 = Buffer 1
$2248-224F = Buffer 2
Arithmetic Control
$2250 (#$00, W, x)
------OO
O = operation
00 = Multiplication
01 = Division
10 = Cumulative sum
Arithmetic Parameters: Multiplicand / Dividend
$2251
$2252 (#$xx, W, x)
NNNNNNNN NNNNNNNN
N = Signed 16 bit data
Arithmetic Parameters: Multiplier / Divisor
$2253
$2254 (#$xx, W, x)
NNNNNNNN NNNNNNNN
N = 16 bit data
N = Signed if multiplication
N = Unsigned if division
Variable-Length BIT Processing
$2258 (#$xx, W, x)
H---VVVV
H = Read mode
1 = Auto increment
0 = Fixed
VVVV = Length of previously stored data
0000 = 16
other values = Literal
Variable-Length BIT Game Pack ROM Start Address
$2259
$225A
$225B (#$xx, W, x)
AAAAAAAA AAAAAAAA AAAAAAAA
A = ROM start address
Execution begins on write to $225B
SA-1 Read Registers
Super Nintendo CPU Flag Read
$2300 (#$xx, x, r)
IVDNmmmm
I = SA-1 IRQ
0 = No Interrupt
1 = Interrupt
V = SNES IRQ vector setting
0 = ROM
1 = SIV register
D = Character conversion DMA IRQ flag
0 = No Interrupt
1 = Interrupt
N = SNES NMI vector setting
0 = ROM
1 = SNV register
mmmm = Messages from SA-1 CPU
SA-1 CPU Flag Read
$2301 (#$xx, x, R)
ITDNmmmm
I = SNES IRQ flag
0 = No Interrupt
1 = Interrupt
T = IRQ from timer
0 = No Interrupt
1 = Interrupt
D = DMA IRQ flag
0 = No Interrupt
1 = Interrupt at end of DMA
N = SNES NMI vector setting
0 = No NMI
1 = NMI
mmmm = Messages from SNES CPU
H-Count Read
$2302
$2303 (#$xx, x, R)
HHHHHHHH -------H
In HV mode values are 0 to 340
In linear mode values are 0 to 511(lower 9 bits)
V-Count Read
$2304
$2305 (#$xx, x, R)
HHHHHHHH -------H
In HV mode values are 0 to 261(NTSC) or 0 to 311(PAL)
In linear mode values are 0 to 511(upper 9 bits)
Arithmetic Result Product / Quotient / Accumulative Sum
$2306
$2307
$2308
$2309
$230A (#$xx, x, R)
Multiplication = $2306-2309 signed
Division = $2306-2307 signed
Division remainder = $2308-2309 unsigned
Cumulative sum = $2306-230A signed
Arithmetic Overflow Flag
$230B (#$xx, x, R)
O-------
O = Overflow
1 = Overflow
0 = No Overflow
Variable-Length Data Read Port
$230C
$230D (#$xx, x, R)
16 bit results from $2258
Version Code Register
$230E
SA-1 Version.