The BS-X cartridge has a MMIO included in Memory 00-0f:5000. (Info taken from bsnes and sd2snes' verilog source)
They all do different things to the Memory, and is NECESSARY, to run games, and other stuff.
We will call them from r00 to r0f. Those have only one bit that can be set.
MCC Registers (ikari_01)
BS-X MCC registers
==================
There are 16 1-bit registers. A register is written or read via the MSB of the data bus.
The registers are mapped at 0n:5xxx where n is the register number and x is "don't care".
r00: ? (doesn't reflect the value written)
r01: ? (contrary to existing documents doesn't seem to have any effect on Flash/PSRAM selection)
r02: 0=LoROM, 1=HiROM; applies to PSRAM and memory pack mapping
r03: Enable PSRAM in low memory banks (00-7D)
r04: Enable PSRAM in high memory banks (80-FF)
r05: PSRAM bank select (Bit 0)
r06: PSRAM bank select (Bit 1)
r07: Map cartridge ROM to 00-3f:8000-ffff, always mapped as LoROM
r08: Map cartridge ROM to 80-bf:8000-ffff, always mapped as LoROM
r09: "Disable" memory pack in low memory banks
r0a: "Disable" memory pack in high memory banks
r0b: Memory pack "disable" bank select
r0c: Memory pack write enable
r0d: ? (possibly also memory pack write related but not necessary for writing to flash)
r0e: writing any value commits changes made to r01-r0d (doesn't reflect the value written)
r0f: strange things happen, apparently the MCC assumes A23-A19 = 0 when set (doesn't reflect the value written, takes effect immediately without commit)
Reset state
===========
r01=0
r02=1
r03=1
r04=0
r05=1
r06=1
r07=1
r08=1
r09=1
r0a=0
r0b=1
r0c=0
r0d=0
PSRAM mapping
=============
PSRAM is mapped to the banks selected by r03-r06.
r03 and r04 determine whether to map PSRAM to the general area of bank 00-7d or 80-ff respectively.
Both may be enabled at the same time.
r05 and r06 determine the location itself.
For r02=0 ("LoROM"):
PSRAM content is mapped according to the LoROM model.
For banks above 40/C0 the lower and upper halves are identical.
r03=1 r04=1
r05=0 r06=0: 00-0F 80-8F
r05=1 r06=0: 20-2F A0-AF
r05=0 r06=1: 40-4F C0-CF
r05=1 r06=1: 60-6F E0-EF
ALWAYS: 70-7D F0-FF * 0000-7FFF! (8 banks, mirrored)
For r02=1 ("HiROM"):
PSRAM content is mapped according to the HiROM model.
For banks below 40/C0 half of the data per bank is missing.
r03=1 r04=1
r05=0 r06=0: 40-47 C0-C7
r05=1 r06=0: 50-57 D0-D7
r05=0 r06=1: 60-67 E0-E7
r05=1 r06=1: 70-77 F0-F7
ALWAYS: 20-3F A0-BF * 6000-7FFF! (8 banks, mirrored, from offset 6000 of PSRAM)
20:6000 maps to offset 6000 of PSRAM, 21:6000 to 16000, etc.
Memory pack mapping:
====================
This mapping applies unless it is altered by any of the registers.
r02=0:
00-3f:8000-ffff (as LoROM)
40-7d:0000-ffff (upper and lower halves of banks identical)
80-bf:8000-ffff (as LoROM)
c0-ff:0000-ffff (upper and lower halves of banks identical)
r02=1:
00-3f:8000-ffff (the lower half of each ROM page is inaccessible)
40-7d:0000-ffff (linear)
80-bf:8000-ffff (the lower half of each ROM page is inaccessible)
c0-ff:0000-ffff (linear)
r09/0a/0b behaviour:
====================
r09 and r0a disable a certain memory area where the memory pack would normally be mapped.
r0b can be used to shift the location of the "hole". Like PSRAM mapping, r09 and r0a can be combined.
Accessing the mapped area returns an open bus value.
The purpose of this is unknown, maybe it was intended to address a secondary ROM chip or memory pack chip.
In that fashion r0d might be "secondary flash write enable" but that is pure speculation.
r09=1 r0b=0:
r02=0: 00-1f:8000-ffff
r02=1: 00-0f:8000-ffff; 40-4f:0000-ffff
r09=1 r0b=1:
r02=0: 40-5f:0000-ffff
r02=1: 20-2f:8000-ffff; 60-6f:0000-ffff
r0a=1 r0b=0:
r02=0: 80-9f:8000-ffff
r02=1: 80-8f:8000-ffff; c0-cf:0000-ffff
r0a=1 r0b=1:
r02=0: c0-df:0000-ffff
r02=1: a0-af:8000-ffff; e0-ef:0000-ffff
Priority for enable flags (same memory location):
=================================================
Cart ROM > PSRAM > "hole" > memory pack
Available Memory Types:
=======================
SRAM, PSRAM, ROM, MP(memory pack), OPEN
unspecified regions are always open bus
00-0F:8000-FFFF PSRAM, ROM, MP, OPEN
10-17:5000-5FFF SRAM
10-1F:8000-FFFF ROM, MP, OPEN
20-3F:6000-7FFF PSRAM, OPEN
20-2F:8000-FFFF PSRAM, ROM, MP, OPEN
30-3F:8000-FFFF ROM, MP
40-47:0000-FFFF PSRAM, MP, OPEN
48-4F:0000-FFFF PSRAM, MP, OPEN
50-57:0000-FFFF PSRAM, MP, OPEN
58-5F:0000-FFFF MP, OPEN
60-67:0000-FFFF PSRAM, MP, OPEN
68-6F:0000-FFFF PSRAM, MP, OPEN
70-7D:0000-7FFF PSRAM, MP, OPEN
70-77:8000-FFFF PSRAM, MP
78-7D:8000-FFFF MP
80-8F:8000-FFFF PSRAM, ROM, MP, OPEN
90-9F:8000-FFFF ROM, MP, OPEN
A0-BF:6000-7FFF PSRAM
A0-AF:8000-FFFF PSRAM, ROM, MP, OPEN
B0-BF:8000-FFFF ROM, MP
C0-C7:0000-FFFF PSRAM, MP, OPEN
C8-CF:0000-FFFF PSRAM, MP, OPEN
D0-D7:0000-FFFF PSRAM, MP, OPEN
D8-DF:0000-FFFF MP, OPEN
E0-E7:0000-FFFF PSRAM, MP, OPEN
E8-EF:0000-FFFF PSRAM, MP, OPEN
F0-FF:0000-7FFF PSRAM, MP
F0-F7:8000-FFFF PSRAM, MP
F8-FF:8000-FFFF MP
Information worked out by ikari and Seru-Kun.
MCC Registers (nocash)
MCC Satellaview BIOS Cart Memory Controller Chip
Basically, the MCC chip contains sixteen 1-bit I/O ports (accessed via
[00h-0Fh:5000h].bit7):
0 DATAPAK Ready IRQ Flag (0=None, 1=IRQ) (Write any value: Acknowledge)
1 DATAPAK Ready IRQ Enable (0=Disable, 1=Enable)
2 Mapping for PSRAM/EXTMEM/DATAPAK (0=LoROM, 1=HiROM)
3 PSRAM Enable for Slow Memory area (banks 00h-7Dh)
4 PSRAM Enable for Fast Memory area (banks 80h-FFh)
5 PSRAM Location Bit0 (offset within bank 00h-7Dh/80h-FFh)
6 PSRAM Location Bit1 (offset within bank 00h-7Dh/80h-FFh)
7 BIOS Enable for Slow Memory area (at 00h-3Fh:8000h-FFFFh) ;\always
8 BIOS Enable for Fast Memory area (at 80h-BFh:8000h-FFFFh) ;/LoROM
9 EXTMEM Enable for Slow Memory area (banks 00h-7Dh)
10 EXTMEM Enable for Fast Memory area (banks 80h-FFh)
11 EXTMEM Location (offset within bank 00h-7Dh/80h-FFh)
12 DATAPAK Write Enable (0=Read Only, 1=Allow Read/Write Access)
13 Unknown (isn't FLASH /WP pin... maybe EXTMEM Write Enable?)
14 Write any value: Apply changes to Bit2-13 (read: always 0)
15 Access Hidden Bits (0=Normal, 1=Access Hidden Bits/unknown purpose)
That sixteen ports are accessed via 4bit INDEX(0..0Fh) and 1bit DATA (0..1),
however, internally, the MCC chip does contain a total of 35 used bits:
lastwrite[N] ;14 bits used (bit1-13,15)
applied[N] ;12 bits used (bit2-13)
hidden[N] ;8 bits used (bit0-7)
irq_flag ;1 bit used (bit0)
Writing "[INDEX:5000h]=DATA*80h" does internally work as so:
if lastwrite[0Fh]=1 then hidden[INDEX and 07h]=DATA
lastwrite[INDEX]=DATA ;<-- this must be done AFTER the above step!
if INDEX=00h then irq_flag=0 ;<-- XXX this done also if lastwrite[0Fh]=1?
if INDEX=0Eh then applied[02h..0Dh]=lastwrite[02h..0Dh]
Reading "DATA=[INDEX:5000h]/80h" does internally work as so:
if lastwrite[0Fh]=0 and INDEX=00h then DATA=irq_flag
if lastwrite[0Fh]=0 and INDEX=01h then DATA=lastwrite[01h]
if lastwrite[0Fh]=0 and INDEX=02h..0Dh then DATA=applied[INDEX]
if lastwrite[0Fh]=0 and INDEX=0Eh..0Fh then DATA=0
if lastwrite[0Fh]=1 then DATA=hidden[INDEX and 07h]
Reading the whole 16bits after reset returns following intial values:
After Reset: 0BECh ;\initial "lastwrite" and "applied" are same
After Apply: 0BECh ;/ (bit2-3, bit5-9, and bit11 enabled)
After Hidden Access: 3F3Fh ;-3Fh on power-up, but NOT reset upon /RESET
Note: hidden[7] can be set to 1 only AFTER and WHILE lastwrite[F]=1.
Priority for overlapping memory locations
Prio Name Size Notes
1 BIOS 1024K (highest priority, if enabled)
2 PSRAM 512K
3 EXTMEM - (always open bus; no such memory chip installed)
4 DATAPAK 1024K (open bus if no datapak connected) (always enabled)
- SRAM 32K (always mapped, can't overlap with other areas)
Note: DATAPAK is on an external cartridge, size is usually 1MByte FLASH.
SRAM and I/O Port Mapping (always mapped, can't overlap with other areas)
00h-0Fh:5000h, Bit7 ;-MMC Bits 0-15 (or 16-31 when selecting 2nd page)
00h-0Fh:5000h, Bit0-6 ;-open bus (MCC chip connects only to D7)
00h-0Fh:5001h-5FFFh ;-Mirrors of above MMC Bits
10h-17h:5000h-5FFFh ;-SRAM (battery backed) (mapped in eight 4K banks)
18h-3Fh:5000h-5FFFh ;\
80h-BFh:5000h-5FFFh ; open bus
00h-1Fh:6000h-6FFFh ;
80h-9Fh:6000h-6FFFh ;/
20h-3Fh:6000h-6FFFh ;\open bus in LoROM mode, or PSRAM in HiROM mode
A0h-BFh:6000h-6FFFh ;/
BIOS Mapping (Priority 1, highest) (MCC Bits 7,8)
Bit7=1 (Slow Area) Bit8=1 (Fast Area)
00h-3Fh:8000h-FFFFh 80h-BFh:8000h-FFFFh
BIOS ROM is always mapped as LoROM (the ROM address lines are hardwired to SNES
bus, so the MCC chip can't change them).
PSRAM Mapping (Priority 2) (MCC Bits 2,3,4,5,6)
For Bit2=0 (LoROM):
Bit6-5 Bit3=1 (Slow Area) Bit4=1 (Fast Area)
0 00h-0Fh:8000h-FFFFh 80h-8Fh:8000h-FFFFh ;\in upper 32K only
1 20h-2Fh:8000h-FFFFh A0h-AFh:8000h-FFFFh ;/
2 40h-4Fh:0000h-FFFFh C0h-CFh:0000h-FFFFh ;\same in upper/lower 32K
3 60h-6Fh:0000h-FFFFh E0h-EFh:0000h-FFFFh ;/
- 70h-7Dh:0000h-7FFFh F0h-FFh:0000h-7FFFh ;-in lower 32K only
For Bit2=1 (HiROM):
Bit6-5 Bit3=1 (Slow Area) Bit4=1 (Fast Area)
0 00h-07h:0000h-FFFFh 80h-87h:0000h-FFFFh ;\
1 10h-17h:0000h-FFFFh 90h-97h:0000h-FFFFh ; only upper 32K half
2 20h-27h:0000h-FFFFh A0h-A7h:0000h-FFFFh ; of full 64K banks
3 30h-37h:0000h-FFFFh B0h-B7h:0000h-FFFFh ;/
0 40h-47h:0000h-FFFFh C0h-C7h:0000h-FFFFh ;\
1 50h-57h:0000h-FFFFh D0h-D7h:0000h-FFFFh ; full 64K banks
2 60h-67h:0000h-FFFFh E0h-E7h:0000h-FFFFh ;
3 70h-77h:0000h-FFFFh F0h-F7h:0000h-FFFFh ;/
- 20h-3Fh:6000h-7FFFh A0h-BFh:6000h-7FFFh ;-8K snippets
The 8K snippets in bank 20h-27h/A0h-A7h are taken from PSRAM offset 006000h,
016000h, .., 076000h. The same snippets are also mirrored in bank
28h-3Fh/A8h-BFh.
The four special regions (at 0000h-7FFFh and 6000h-7FFFh) are affected only by
MCC Bits 2,3,4 (not affected by MCC Bits 5,6).
EXTMEM Mapping (Priority 3) (MCC Bits 2,9,10,11)
For Bit2=0 (LoROM):
Bit11 Bit9=1 (Slow Area) Bit10=1 (Fast Area)
Bit11=0 00h-1Fh:8000h-FFFFh 80h-9Fh:8000h-FFFFh ;-in upper 32K only
Bit11=1 40h-5Fh:0000h-FFFFh C0h-DFh:0000h-FFFFh ;-same in upper/lower 32K
For Bit2=1 (HiROM):
Bit11 Bit9=1 (Slow Area) Bit10=1 (Fast Area)
Bit11=0 00h-0Fh:8000h-FFFFh 80h-8Fh:8000h-FFFFh ;\only upper 32K half
Bit11=1 20h-2Fh:8000h-FFFFh A0h-AFh:8000h-FFFFh ;/
Bit11=0 40h-4Fh:0000h-FFFFh C0h-CFh:0000h-FFFFh ;\full 64K banks
Bit11=1 60h-6Fh:0000h-FFFFh E0h-EFh:0000h-FFFFh ;/
EXTMEM would be some extra memory chip which isn't installed in existing carts.
In result, the corresponding memory area will just become open bus when trying
to enable EXTMEM.
DATAPAK Mapping (Priority 4, lowest) (MCC Bit 2) (and Bit 12: Write Enable)
For Bit2=0 (LoROM):
Always (Slow Area) Always (Fast Area)
00h-3Fh:8000h-FFFFh 80h-BFh:8000h-FFFFh ;-in upper 32K only ;1st 2MB?
40h-7Dh:0000h-FFFFh C0h-FFh:0000h-FFFFh ;-same in upper/lower 32K ;2nd 2MB?
For Bit2=1 (HiROM):
Always (Slow Area) Always (Fast Area)
00h-3Fh:8000h-FFFFh 80h-BFh:8000h-FFFFh ;-only upper 32K half of 64K banks
40h-7Dh:0000h-FFFFh C0h-FFh:0000h-FFFFh ;-full 64K banks ;full 4MB
DATAPAK is always enabled and mapped to the entire ROM area (unless it's
overlapped by higher-priority memory blocks).