This table describes how each of the P register's flags change when different instructions are run. An empty cell denotes that the flag is unchanged. Effects are lifted from undisbelievers' 65816 opcode page.

UNDER CONSTRUCTION (may have mistakes)

Logic & Arithmetic

Mnemonic N V M X D I Z C E B
ADC Most significant bit of sum Signed overflow of sum Set if sum is zero Carry from ALU (bit 8/16 of result)
SBC Most significant bit of difference Signed overflow of difference Set if difference is zero Carry from ALU (bit 8/16 of result) (set if borrow not required)
AND Most significant bit of conjunction Set if conjunction is zero
ORA Most signifciant bit of disjunction Set if disjunction is zero
EOR Most significant bit of exclusive disjunction Set if exclusive disjunction is zero
ASL Most significant bit of result Set if the result is zero Most significant bit of original Memory
LSR cleared Set if the result is zero Bit 0 of original memory
BIT (not immediate) most significant bit of memory Second most significant bit of memory Set if logical AND of memory and Accumulator is zero
BIT (immediate) Set if logical AND of memory and Accumulator is zero

Clear Status Flags

Mnemonic N V M X D I Z C E B
CLC 0
CLD 0
CLI 0
CLV 0

Comparison

Mnemonic N V M X D I Z C E B
CMP Most significant bit of result Set if the result is zero (Set if A == M) Carry from ALU (Set if A >= M)
CPX Most significant bit of result Set if the result is zero (Set if X == M) Carry from ALU (Set if X >= M)
CPY Most significant bit of result Set if the result is zero (Set if Y == M) Carry from ALU (Set if Y >= M)

Increment/Decrement

Mnemonic N V M X D I Z C E B
DEC Most significant bit of Peano predecessor Set if the result is zero
DEX Most significant bit of Peano predecessor Set if the result is zero
DEY Most significant bit of Peano predecesor Set if the result is zero
INC Most significant bit of Peano successor Set if the result is zero
INX Most significant bit of Peano successor Set if the result is zero
INY Most significant bit of Peano successor Set if the result is zero

Jumps

Mnemonic N V M X D I Z C E B
JMP
JML
JSR
JSL

Load

Mnemonic N V M X D I Z C E B
LDA Most significant bit of Accumulator Set if the Accumulator is zero
LDX Most significant bit of X Set if the X is zero
LDY Most significant bit of Y Set if the Y is zero

Block Move

Mnemonic N V M X D I Z C E B
MVN
MVP

Push to Stack

Mnemonic N V M X D I Z C E B
PEA
PEI
PER
PHA
PHB
PHD
PHK
PHP
PHX
PHY

Pull from Stack

Mnemonic N V M X D I Z C E B
PLA Most significant bit of register set if the register is zero
PLB Most significant bit of register set if the register is zero
PLD Most significant bit of register set if the register is zero
PLP (native mode) pulled from stack pulled from stack pulled from stack pulled from stack pulled from stack pulled from stack pulled from stack
PLP (emulation mode) pulled from stack pulled from stack 1 1 pulled from stack pulled from stack pulled from stack
PLX Most significant bit of register set if the register is zero
PLY Most significant bit of register set if the register is zero

Set/Reset Status bits

Mnemonic N V M X D I Z C E B
REP (native mode) cleared when n bit of operand set cleared when v bit of operand set cleared when m bit of operand set cleared when x bit of operand set cleared when d bit of operand set cleared when i bit of operand set cleared when z bit of operand set cleared when c bit of operand set
REP (emulation mode) cleared when n bit of operand set cleared when v bit of operand set 1 1 cleared when d bit of operand set cleared when i bit of operand set cleared when z bit of operand set cleared when c bit of operand set
SEP or'd with n bit of operand or'd with v bit of operand or'd with m bit of operand or'd with x bit of operand or'd with d bit of operand or'd with i bit of operand or'd with z bit of operand or'd with c bit of operand

Rotation

Mnemonic N V M X D I Z C E B
ROL Most significant bit of result set if the result is zero Most significant bit of original memory
ROR Most significant bit of result set if the result is zero Most significant bit of original memory

Return

Mnemonic N V M X D I Z C E B
RTI (native mode) pulled from stack pulled from stack pulled from stack pulled from stack pulled from stack pulled from stack pulled from stack pulled from stack
RTI (emulation mode) pulled from stack pulled from stack 1 1 pulled from stack pulled from stack pulled from stack pulled from stack
RTS
RTL

Set Status Flags

Mnemonic N V M X D I Z C E B
SEC 1
SED 1
SEI 1

Store

Mnemonic N V M X D I Z C E B
STA
STX
STY
STZ

Transfer Registers

Mnemonic N V M X D I Z C E B
TAX Most significant bit of register Set if the register is zero
TAY Most significant bit of register Set if the register is zero
TCD Most significant bit of register Set if the register is zero
TDC Most significant bit of register Set if the register is zero
TSC Most significant bit of register Set if the register is zero
TSX Most significant bit of register Set if the register is zero
TXA Most significant bit of register Set if the register is zero
TXY Most significant bit of register Set if the register is zero
TYA Most significant bit of register Set if the register is zero
TYX Most significant bit of register Set if the register is zero
TCS
TXS

Test and Set/Reset Memory Bits against Accumulator

Mnemonic N V M X D I Z C E B
TRB Set if logical AND of memory and Accumulator is zero
TSB Set if logical AND of memory and Accumulator is zero

Exchange bits

Mnemonic N V M X D I Z C E B
XBA bit 7 of the new Accumulator (even in 16-bit mode) Set if bits 0-7 of the new Accumulator are 0 (even in 16 bit mode)
XCE set if enabling native mode set if enabling native mode Previous E flag Previous C flag

Branches

Mnemonic N V M X D I Z C E B
BBC
BCS
BEQ
BNE
BMI
BPL
BVC
BVS
BRA
BRL

Misc

Mnemonic N V M X D I Z C E B
WAI
WDM
STP
NOP
BRK 0 1
COP 0 1