Hardware Specification to SWC & SMC Programmer Only
- DRAM - 28 Mega Bits Maximum Available.
- SRAM - 256K Bits. (Battery Backup)
- ROM - 128K Bits. (Firmware)
- Floppy Drive Interface
- Motorola MCS3201 Chip. (NEC 765a Compatible)
- Compatible With IBM PC/at and XT Disk Drive System.
- Supports 3.5" or 5.25" Floppy Disk Drive.
- Db-25 Female Connector. (Non-Standard)
- Supports Only Non-Dma Mode. (Polling)
5. Parallel Port Interface
- 8 Bits Input, 4 Bits Output, 1 Bit Handshake.
- DB-25 Female Connector.
- Use Male DB-25 to Male DB-25 Cable Connect to IBM PC Parallel Port.
Software Specification & Feature
Registers
Floppy Drive I/O
================
C000R : Input Register
Bit 7 : MCS3201 IRQ Signal
Bit 6 : Drive 'Index' Signal (Disk Insert Check)
C002W : Digital Output Register
C004R : Main Status Register
C005RW: Data Register
C007R : Digital Input Register
C007W : Diskette Control Register
* Consult the MCS3201 Data Sheet for More Detailed Information
Parallel I/O
============
C008R : Bit 0-7 : Parallel Data Input (Reading this register will reverse the busy flag.)
C008W : Bit 0-3 : Parallel Data Output
Bit 0 : 0=Mode 20, 1=Mode 21 (DRAM Mapping)
Bit 1 : 0=Mode 1, 1=Mode 2 (SRAM Mapping)
C009R : Busy Flag, Bit 7 (EP1810 Version)
C000R : Busy Flag, Bit 5 (FC9203 Version)
Page Select
===========
E000W : Memory Page 0
E001W : Memory Page 1
E002W : Memory Page 2
E003W : Memory Page 3
Mode Select
===========
E004W : System Mode 0 (BIOS Mode, Power on Default)
E005W : System Mode 1 (Play Cartridge)
E006W : System Mode 2 (Cartridge Emulation 1)
E007W : System Mode 3 (Cartridge Emulation 2)
Others
======
E008W : 44256 DRAM Type (FOR 2,4,6,8 Mega DRAM Card)
E009W : 441000 DRAM Type (FOR 8,16,24,32 Mega DRAM Card)
E00CW : Enable Cartridge Page Mapping at A000-BFFF (SYS MODE 0)
Disable Cartridge Mapping at Bank 20-5F, A0-DF (SYS MODE 2,3)
E00DW : Enable SRAM Page Mapping at A000-BFFF (SYS MODE 0)
Enable Cartridge Mapping at Bank 20-5F, A0-DF. (SYS MODE 2,3)
* The Bank Address of the above registers is 00-7D, 80-FF
* The above registers are available only in System Mode 0 (BIOS Mode)
* [Mode Select] Registers also available in System Mode 2
Memory Mapping
System Mode 0
=============
bb2000-bb3FFFRW: SRAM or Cartridge Page Mapping, bb-40-7D,C0-FF
bb8000-bb9FFFRW: DRAM Page Mapping, bb-00-7D,80-FF
bbA000-bbBFFFRW: SRAM or CARTRIDGE PAGE MAPPING, bb=00-7D, 80-FF.
bbC000- RW: I/O Registers, bb=00-7D, 80-FF. (Registers)
bbE000-bbFFFFR : ROM Page Mapping, BB=0-1. (Firmware)
* 1 Page = 8K Bytes, 1 Bank = 4 Pages.
* bb:00-0F = 4 Mega Bytes.
* bb:00-1F = 8 Mega Bytes.
* bb:00-2F = 12 Mega Bytes.
* bb:00-3F = 16 Mega Bytes.
...
System Mode 1
=============
bb0000-bb7FFFR : Cartridge Mapping, bb=40-7D, C0-FF. (Mode 21)
bb8000-bbFFFFR : Cartridge Mapping, bb=00-7D, 80-FF. (Mode 20,21)
System Mode 2
=============
bb0000-bb7FFFR : DRAM Mapping, bb=40-70, C0-E0. (Mode 21)
bb8000-bbFFFFR : DRAM Mapping, bb=00-70, 80-E0. (Mode 20,21)
708000-70FFFFRW: SRAM Mode 1 Mapping.
306000-307FFFRW: SRAM Mode 2 Mapping, Page 0.
316000-317FFFRW: SRAM Mode 2 Mapping, Page 1.
326000-327FFFRW: SRAM Mode 2 Mapping, Page 2.
336000-337FFFRW: SRAM Mode 2 Mapping, Page 3.
*bbE004-bbE007W: Mode Select Registers, bb=00-7D, 80-FF.
System Mode 3
=============
bb0000-bb7FFFR : DRAM Mapping, bb=40-6F, C0-DF. (Mode 21)
bb8000-bbFFFFR : DRAM Mapping, bb=00-6F, 80-DF. (Mode 20,21)
708000-70FFFFRW: SRAM Mode 1 Mapping.
306000-307FFFRW: SRAM Mode 2 Mapping, Page 0.
316000-317FFFRW: SRAM Mode 2 Mapping, Page 1.
326000-327FFFRW: SRAM Mode 2 Mapping, Page 2.
336000-337FFFRW: SRAM Mode 2 Mapping, Page 3.
* Mode 21
Even DRAM Bank is mapped to bb0000-bb7FFF.
Odd DRAM Bank is mapped to bb8000-bbFFFF.
Parallel I/O Protocol
Protocol Used in PC
===================
* Byte Output Procedure
Wait Busy Bit = 1 Status Port Bit7 (Hex n79, n7D)
Write One Byte Data Latch (Hex n78, n7C)
Reverse Strobe Bit Control Port Bit0 (Hex n7A, n7E)
* Byte Input Procedure
Wait Busy Bit = 0 Status Port Bit7 (Hex n79, n7D)
Read Low 4 Bits of Byte Status Port Bit3-6 (Hex n79, n7D)
Reverse Strobe Bit Control Port Bit0 (Hex n7A, n7E)
Wait Busy Bit = 0 Status Port Bit7 (Hex n79, n7D)
Read High 4 Bits of Byte Status Port Bit3-6 (Hex n79, n7D)
Reverse Strobe Bit Control Port Bit0 (Hex n7A, n7E)
* 5 Types of Command
* Command Length = 9 Bytes
* Command Format
Byte 1 D5 ID Code 1
Byte 2 AA ID Code 2
Byte 3 96 ID Code 3
Byte 4 00|01|04|05|06 Command Code
Byte 5 al Low Byte of Address
Byte 6 ah High Byte of Address
Byte 7 ll Low Byte of Data Length
Byte 8 lh High Byte of Data Length
Byte 9 cc Checksum = 81 ^ Byte4 ^ Byte5 ^ Byte6 ^ Byte7 ^ Byte8
* Command [00] : Download Data
al, ah = Address
ll, lh = Data Length
Output Datas After Command
* Command [01] : Upload Data
al, ah = Address
ll, lh = Data Length
Input Datas After Command
* Command [04] : Force SFC Program to JMP
al, ah = Address
* Command [05] : Set Memory Page Number
al Bit 0-1 = Page Number
al Bit 2-7 + ah Bit 0-1 = Bank Number
* Command [06] : Sub Function
al = 0 Initial Device
al = 1 Play Game in DRAM
al = 2 Play Cartridge
Cheat / Password Format
Use the data in the cheat / password to replace the data an the memory offset address.
Game Doctor Gold Finger Format
==============================
20 Bits Address Space Assignment
3 data Bytes per String
Gaaaaaddddddccc
G = Game Doctor Format
aaaaa = Offset Address of game (excluding 512 Bytes header)
dddddd = 3 data Bytes (if the 2nd or the 3rd data is '00', the data remains unchanged at the second or third byte)
ccc = Checksum (Not Used in the SWC or SMC)
Front Far East Format
=====================
24 Bits Address Space Assignment
1 to 36 data Bytes per string
No Checksum
nnaaaaaadd....
nn = Data Byte Length
aaaaaa = Offset Address of game (excluding 512 Bytes header)
dd.... = nn Bytes data (should be nn*2 characters)
File Header
Created by JSI / Front Fareast. 0x200 / 512 bytes length (One Sector)
BYTE
0 - Low Byte of 8K-Bytes Page Counts
1 - High Byte of 8K-Bytes Page Counts
2 - Emulation Mode Select
Bit 76543210
X : 1 = Run in Mode 0 (Jump $8000)
X : 0 = Last File of the Game (Multi File Loading)
X : 0 = Mode 1, 1 = Mode 2 (SRAM Mapping)
X : 0 = Mode 20, 1 = Mode 21 (DRAM Mapping)
Xx : 0 = SRAM off, 1 = Sram 16K, 2 = Sram 64K, 3 = Sram 256K
X : 0 = Run in Mode 3, 1 = Run in Mode 2 (JMP Reset)
X : 0 = Disable, 1 = Enable (External Cartridge Memory Image at Bank 20-5f, a0-df in System Mode 2, 3)
3-7 - Reserved (Should Be '00')
8 - File ID Code 1. (Should Be 'AA')
9 - File ID Code 2. (Should Be 'BB')
10 - Check this byte if ID 1 & 2 match:
'02': Magic Griffin Game File (PC Engine)
'03': Magic Griffin SRAM Data Faile
'04': SWC & SSM Game File (Super Magicom)
'05': SWC & SMC Password, SRAM Data, Saver Data File
'06': SMD Game File (Mega Drive)
'07': SMD Sram Data File
11-511 - Reserved (Should Be '00')
Memory Mode Swap File Format
Description
This is version 1.0 of the format. It does't contain Super Famicom PPU Registers. I plan to support PPU Registers backup in the 'Super Wildcard Plus' and 'Super Wildcard 2' machine (it requires the hardware support for PPU Register backup). So in new machine it will be possible to convert the memory file to a still image in the computer and get an in game screenshot. Also you can view the memory file image on TV through a utility program by Wildcard (thin function may include in the new BIOS for the 2 new machines).
File Length
512 byte Header + 256K bytes Data
Format
Offset Description
=========== ===========
0- 1FF Header
200-201FF 128Kb. CPU Work RAM 7E0000-7FFFFF Image
20200-301FF 64Kb. PPU VRAM Image
30200-3E1FF 56Kb. Reserved
3E200-401FF CPU Register Backup
3E200 P Flag Register
3E201 Data Bank Register
3E202-3 A Register
3E204-5 X Register
3E206-7 Y Register
3E208-9 S Register
3E20A-B Direct Register
WILD CARD MODE BACKUP
3F208-9 C008-9 Register
3F20A Bit 0 of Emulation Mode Select
Originally by JSI, some rough sections reworded from Engrish by Matthew Callis